In our British patent application no. 9607153.5 there is described a data processing management system for executing independent instruction threads an multi-threaded processor. This describes a microprocessor system having a priority of data inputs and outputs and a priority of data processing means. Each data processing means performs operations to execute instructions from at least one of a plurality of instruction threads. The control means selectively routes data between the data inputs and outputs via a selected one of the data processing means. The external interfaces (inputs and outputs) may be interfaces to co-processors which are used to perform other operations. These co-processors and the external interfaces in the microprocessor have to be integrated into the system so that they can be efficiently accessed by instructions running on the microprocessor.
Normally a microprocessor schedules instructions using knowledge about the capabilities of external units or co-processors. However, if a microprocessor is attached to another module with unpredictable behaviour this will not necessarily be possible. It is quite common for co-processors attached to microprocessors not to provide data to the controlling microprocessor about their operation and behaviour. Therefore, a microprocessor sending instructions to a co-processor has no knowledge as to whether or not the co-processor is capable of receiving those instructions. In the case of a multi-threaded system where more than one set of instructions may be provided to more than one co-processor this is particularly important since situations may arise where a number of co-processors are executing their instructions without a problem but another one is for some internal reason blocked and therefore unable to receive further instructions.